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? semiconductor components industries, llc, 2008 may, 2008 ? rev. 0 1 publication order number: NLAS4051S/d NLAS4051S analog multiplexer/ demultiplexer ttl compatible, single ? pole, 8 ? position plus common off the NLAS4051S is an improved version of the mc14051 and mc74hc4051 fabricated in sub ? micron silicon gate cmos technology for lower r ds(on) resistance and improved linearity with low current. this device may be operated either with a single supply or dual supply up to 3.0 v to pass a 6.0 v pp signal without coupling capacitors. when operating in single supply mode, it is only necessary to tie v ee , pin 7 to ground. for dual supply operation, v ee is tied to a negative voltage, not to exceed maximum ratings. features ? improved r ds(on) specifications ? pin for pin replacement for max4051 and max4051a ? one half the resistance operating at 5.0 v ? single or dual supply operation ? single 2.5 ? 5.0 v operation, or dual 3.0 v operation ? with v cc of 3.0 to 3.3 v, device can interface with 1.8 v logic, no translators needed ? address and inhibit logic are over ? voltage tolerant and may be driven up +6.0 v regardless of v cc ? improved linearity over standard hc4051 devices ? space saving tssop package ? this is a pb ? free device figure 1. pin connection (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 no 2 no 4 no 0 no 6 add c add b add a no 1 no 3 com no 7 no 5 inhibit v ee gnd tssop ? 16 dt suffix case 948f marking diagram nlas 4051 alyw a = assembly location l = wafer lot y = year w = work week = pb ? free package ordering information device package shipping ? http://onsemi.com NLAS4051Sdtr2g tssop ? 16 (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. 1 16 1 16 (note: microdot may be in either location)
NLAS4051S http://onsemi.com 2 truth table inhibit address on switches* c b a 1 x don?t care x don?t care x don?t care all switches open 0 0 0 0 com ? no 0 0 0 0 1 com ? no 1 0 0 1 0 com ? no 2 0 0 1 1 com ? no 3 0 1 0 0 com ? no 4 0 1 0 1 com ? no 5 0 1 1 0 com ? no 6 0 1 1 1 com ? no 7 *no and com pins are identical and interchangeable. either may be considered an input or output; signals pass equally well in either direction. figure 2. logic diagram no 4 no 7 inhibit no 6 no 3 add a logic add b add c no 5 no 2 no 1 no 0 com ????????????????????????????????? ????????????????????????????????? maximum ratings ?????????????????????? ?????????????????????? ???? ???? ???????? ???????? ?? ?? ?????????????????????? ?????????????????????? negative dc supply voltage (referenced to gnd) v ee ???????? ???????? ? 7.0 to 0.5 ?? ?? ?????????????????????? ?????????????????????? ???????? ???????? ? 0.5 to 7.0 ? 0.5 to 7.0 ?? ?? ?????????????????????? ?????????????????????? ???????? ???????? ? 0.5 to v cc 0.5 ?? ?? ?????????????????????? ?????????????????????? ???????? ???????? ? 0.5 to 7.0 ?? ?? ?????????????????????? ?????????????????????? ???????? ???????? 50 ?? ?? ?????????????????????? ?????????????????????? ???????? ???????? ? 65 to 150 ?? ?? c ?????????????????????? ?????????????????????? ???????? ???????? ?? ?? c ?????????????????????? ?????????????????????? ???????? ???????? 150 ?? ?? c ?????????????????????? ?????????????????????? ja ???????? ???????? ?? ?? c/w ?????????????????????? ?????????????????????? ???????? ???????? ?? ?? ?????????????????????? ?????????????????????? ???????? ???????? ?? ?? ?????????????????????? ?????????????????????? ? 35% f r ???????? ???????? ? 0 @ 0.125 in ?? ?? ?????????????????????? ?????????????????????? ?????????????????????? ?????????????????????? ???????? ???????? ???????? ???????? 2000 200 1000 ?? ?? ?? ?? ?????????????????????? ?????????????????????? c (note 5) i latchup ???????? ???????? 300 ?? ?? |v ee | 7.0. 2. tested to eia/jesd22 ? a114 ? a. 3. tested to eia/jesd22 ? a115 ? a. 4. tested to jesd22 ? c101 ? a. 5. tested to eia/jesd78.
NLAS4051S http://onsemi.com 3 recommended operating conditions parameter ????? ????? ??????????????????????? ??????????????????????? negative dc supply voltage (referenced to gnd) v ee ??? ??? ? 5.5 ???? ???? ?? ?? ??????????????????????? ??????????????????????? ??????????????????????? ??? ??? ??? ???? ???? ???? ?? ?? ?? ??????????????????????? ??????????????????????? ??? ??? ???? ???? ?? ?? ??????????????????????? ??????????????????????? ??? ??? ???? ???? ?? ?? ??????????????????????? ??????????????????????? ??? ??? ? 55 ???? ???? ?? ?? c ??????????????????????? ??????????????????????? 0.3 v (channel select or enable inputs) v cc = 5.0 v 0.5 v t r , t f ??? ??? ???? ???? ?? ?? ? logic voltage level or a low ? logic input voltage level. dc characteristics ? digital section (voltages referenced to gnd) parameter condition v cc v guaranteed limit unit symbol ? 55 to 25 c 85 c 125 c minimum high ? level input voltage, address and inhibit inputs v ih 2.5 3.0 4.5 5.5 1.75 2.1 3.15 3.85 1.75 2.1 3.15 3.85 1.75 2.1 3.15 3.85 v maximum low ? level input voltage, address and inhibit inputs v il 2.5 3.0 4.5 5.5 .45 0.9 1.35 1.65 .45 0.9 1.35 1.65 .45 0.9 1.35 1.65 v maximum input leakage current, address or inhibit inputs v in = 6.0 or gnd i in 0 v to 6.0 v 0.1 1.0 1.0 a maximum quiescent supply current (per package) address, inhibit and v is = v cc or gnd i cc 6.0 4.0 40 80 a dc electrical characteristics ? analog section ????????? ????????? ????????? ????????? ????????? ????????? ???? ???? ???? ??? ??? ??? ?? ?? ?? ?????????? ?????????? ?? ?? ?? ????? ????? ? 55 to 25 c ??? ??? 85 c ???? ???? 125 c ????????? ????????? ????????? ????????? maximum ?on? resistance (note 7) ????????? ????????? ????????? ????????? ??? ??? ??? ??? ?? ?? ?? ?? ? 3.0 ????? ????? ????? ????? ??? ??? ??? ??? ???? ???? ???? ???? ?? ?? ?? ?? ????????? ????????? ????????? maximum difference in ?on? resistance between any two channels in the same package ????????? ????????? ????????? ? (v cc ? v ee ), v is = 3.0 v |i s | = 10 ma, v is = 2.0 v r on ??? ??? ??? ?? ?? ?? ? 3.0 ????? ????? ????? ??? ??? ??? ???? ???? ???? ?? ?? ?? on resistance flatness |i s | = 10 ma v com = 1, 2, 3.5 v v com = 2, 0, 2 v r flat(on) 4.5 3.0 3.0 4 2 4 2 5 3 maximum off ? channel leakage current switch off v in = v il or v ih v io = v cc ? 1.0 v or v ee +1.0 v (figure 17) i nc(off) i no(off) 6.0 3.0 0 ? 3.0 0.1 0.1 5.0 5.0 100 100 na maximum on ? channel leakage current, channel ? to ? channel switch on v io = v cc ? 1.0 v or v ee +1.0 v (figure 17) i com(on) 6.0 3.0 0 ? 3.0 0.1 0.1 5.0 5.0 100 100 na 7. at supply voltage (v cc ) approaching 2.5 v the analog switch on ? resistance becomes extremely non ? linear. therefore, for low voltage operation it is recommended that these devices only be used to control digital signals.
NLAS4051S http://onsemi.com 4 ac characteristics (input t r = t f = 3 ns) ????????? ????????? ????????? ????????? parameter ????????? ????????? ????????? ????????? ???? ???? ???? ???? ?? ?? ?? ?? ??? ??? ??? ??? ?????????? ?????????? ?? ?? ?? ?? ????? ????? ? 55 to 25 c ??? ??? ??? 85 c ???? ???? ???? 125 c ??? ??? ??? ??? minimum break ? before ? make time v in = v il or v ih v is = v cc r l = 300 c l = 35 pf (figure 19) t bbm 3.0 4.5 3.0 0.0 0.0 ? 3.0 1.0 1.0 1.0 6.5 5.0 3.5 ? ? ? ? ? ? ns *typical characteristics are at 25 c. ac characteristics (c l = 35 pf, input t r = t f = 3 ns) parameter symbol v cc v v ee v guaranteed limit unit ? 55 to 25 c 85 c 125 c min typ max min max min max transition time (address selection time) (figure 18) t trans 2.5 3.0 4.5 3.0 0 0 0 ? 3.0 22 20 16 16 40 28 23 23 45 30 25 25 50 35 30 28 ns turn ? on time (figures 14, 15, 20, and 21) inhibit to n o or n c t on 2.5 3.0 4.5 3.0 0 0 0 ? 3.0 22 18 16 16 40 28 23 23 45 30 25 25 50 35 30 28 ns turn ? off time (figures 14, 15, 20, and 21) inhibit to n o or n c t off 2.5 3.0 4.5 3.0 0 0 0 ? 3.0 22 18 16 16 40 28 23 23 45 30 25 25 50 35 30 28 ns typical @ 25 c, v cc = 5.0 v maximum input capacitance, select inputs c in 8 pf analog i/o c no or c nc 10 common i/o c com 10 feedthrough c (on) 1.0 additional application characteristics (gnd = 0 v) parameter condition v cc v v ee v typ unit symbol 25 c maximum on ? channel bandwidth or minimum frequency response v is = ? (v cc ? v ee ) source amplitude = 0 dbm (figures 10 and 22) bw 3.0 4.5 6.0 3.0 0.0 0.0 0.0 ? 3.0 80 90 95 95 mhz off ? channel feedthrough isolation f =100 khz; v is = ? (v cc ? v ee ) source = 0 dbm (figures 12 and 22) v iso 3.0 4.5 6.0 3.0 0.0 0.0 0.0 ? 3.0 ? 93 ? 93 ? 93 ? 93 db maximum feedthrough on loss v is = ? (v cc ? v ee ) source = 0 dbm (figures 10 and 22) v onl 3.0 4.5 6.0 3.0 0.0 0.0 0.0 ? 3.0 ? 2 ? 2 ? 2 ? 2 db charge injection v in = v cc to v ee, f is = 1 khz, t r = t f = 3 ns r is = 0 , c l = 1000 pf, q = c l * v out (figures 16 and 23) q 5.0 3.0 0.0 ? 3.0 9.0 12 pc total harmonic distortion thd + noise f is = 1 mhz, r l = 10 k , c l = 50 pf, v is = 5.0 v pp sine wave v is = 6.0 v pp sine wave (figure 13) thd 6.0 3.0 0.0 ? 3.0 0.10 0.05 %
NLAS4051S http://onsemi.com 5 v is (vdc) temperature ( c) figure 3. i cc versus temp, v cc = 3 v and 5 v i cc (na) ? 40 60 80 20 0 100 ? 20 120 v cc = 3.0 v v cc = 5.0 v 10 1 0.1 100 0.01 0.001 0.0001 0.00001 figure 4. r on versus v cc , temp = 25 c figure 5. typical on resistance v cc = 2.0 v, v ee = 0 v figure 6. typical on resistance v cc = 3.0 v, v ee = 0 v figure 7. typical on resistance v cc = 4.5 v, v ee = 0 v figure 8. typical on resistance v cc = 5.5 v, v ee = 0 v ? 4.0 4.0 6.0 2.0 0 ? 2.0 80 60 40 100 20 0 r on ( ) 2.0 v 3.0 v 4.5 v 5.5 v 0 10 20 30 40 50 0 0.5 1.0 1.5 2.0 2.5 3. 0 125 c 85 c 25 c ? 55 c v com (v) r on ( ) 5 10 15 20 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4. 5 0 0 v com (v) r on ( ) 0 5 10 15 25 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 125 c 85 c 25 c ? 55 c ? 55 c 125 c 85 c 25 c v com (v) r on ( ) 20 v com (v) 40 30 20 50 10 r on ( ) 0 2.0 1.5 1.0 0.5 125 c 85 c 25 c ? 55 c 90 80 70 100 60
NLAS4051S http://onsemi.com 6 figure 9. typical on resistance v cc = 3.3 v, v ee = ? 3.3 v figure 10. bandwidth, v cc = 5.0 v ? 10 frequency (mhz) off isolation 10 db/div 0 0.1 10 1.0 100 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 10 1000 100 10000 0 0.1 0.01 frequency (mhz) distortion (%) 10000 4.5 3.0 3.3 5.5 figure 11. phase shift, v cc = 5.0 v 0.1 10 1.0 100 frequency (mhz) phase shift 18%/div (db) 90 phase shift 72 18 ? 18 ? 54 ? 90 figure 12. off isolation, v cc = 5.0 v figure 13. total harmonic distortion 54 36 0 ? 36 ? 72 125 c 85 c 25 c ? 55 c 0 5 10 15 20 ? 4 ? 20 2 4 v com (v) r on ( ) 25 ? 10 0.1 10 1.0 100 frequency (mhz) bandwidth (db) 0 bandwidth (on ? response) ? 20 ? 30 ? 40 ? 50 50 40 30 20 10
NLAS4051S http://onsemi.com 7 3.0 30 2.5 4.5 35 figure 14. t on and t off versus v cc v cc (volts) figure 15. t on and t off versus temp temperature ( c) time (ns) time (ns) figure 16. charge injection versus com voltage v com (v) q (pc) ? 55 25 125 ? 40 20 15 25 0 034 2 15 t on v cc = 3 v v cc = 5 v 2.5 2.0 1.5 1.0 0.5 0 ? 0.5 10 5 t off t on (ns) t off (ns) v cc = 4.5 v 3.5 4 30 20 15 25 0 10 5 85 ? 55 ? 20 leakage (na) figure 17. switch leakage versus temperature 1 i no(off) temperature ( c) 0.01 25 0.001 0.1 70 85 125 i com(on) i com(off) v cc = 5.0 v 10 100 t a = 25 c 50% 50% 90% 10% 0 v output input 35 pf output address select pin figure 18. channel selection propagation delay 300 v cc v cc 0.1 f v out v ee v ee v cc t trans t trans
NLAS4051S http://onsemi.com 8 90% 90% 50% 50% output input 0 v 35 pf enable input open dut output 90% gnd output gnd input 35 pf output address select pin dut 300 v cc v cc 90% of v oh t on t off v oh v cc 0.1 f t bmm v out gnd v cc 300 v out 0.1 f figure 19. t bbm (time break ? before ? make) figure 20. t on /t off 50% 50% 10% 10% 0 v input output 35 pf output enable input open dut v cc t on t off v cc 300 v out v cc v ol figure 21. t on /t off
NLAS4051S http://onsemi.com 9 transmitted output input reference dut channel switch address and inhibit/s test socket is normalized. off isolation is measured across an off channel. on loss is the bandwidth of an on switch. v iso , bandwidth and v onl are independent of the input signal direction. v iso = off channel isolation = 20 log for v in at 100 khz v onl = on channel loss = 20 log for v in at 100 khz to 50 mhz bandwidth (bw) = the frequency 3 db below v onl 50 50 generator 50 v out v in v out v in figure 22. off channel isolation/on channel loss (bw)/crosstalk (on channel to off channel)/v onl off on off output open dut v out v cc gnd v in c l figure 23. charge injection: (q) v in output typical operation 8 7 16 +3.0 v 8 7 16 +5.0 v figure 24. 5.0 volts single supply v cc = 5.0 v, v ee = 0 figure 25. dual supply v cc = 3.0 v, v ee = ? 3.0 v ? 3.0 v gnd v ee v ee gnd v cc v cc
NLAS4051S http://onsemi.com 10 package dimensions tssop ? 16 case 948f ? 01 issue b ??? ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
NLAS4051S http://onsemi.com 11 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NLAS4051S/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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